Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew

A methodology based on supply voltage scaling for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in this paper. The clock signal is distributed globally at a lower optimum supply voltage. To maintain the speed of the system, a dual supply voltage (dual-V
_DD
) clock distribution network is presented. Level converters are utilized to restore the standard full swing clock signal at the leaves of the low voltage clock distribution network. A novel level converter with low skew, propagation delay, and power consumption characteristics is presented. The optimum supply voltage that minimizes clock skew is 44% lower than the nominal supply voltage in a 0.18mum CMOS technology. The temperature fluctuations induced skew and power consumption of the proposed dualdual-V
_DD
clock distribution network are 74% and 50.8% lower, respectively, as compared to a standard clock distribution network operating at the nominal supply voltage