A Novel Method for Systematic Error Prediction of CMOS Folding and Interpolating ADC

In this paper, the systematic error due to interpolation in CMOS deep sub micron folding and interpolating ADC is studied and a closed form equation is presented to calculate the error as a function of interpolation coefficient, input voltage range and the number of input differential pairs. The amount of INL due to interpolation error can be considered as the lower bound for attainable INL of a specific ADC architecture. A case study for an 8_bit ADC is treated under consideration of different folding and interpolating factors. The trade off between power dissipation and ADC performance is characterized according to input stage characteristics