Low Power Multiplier with Bypassing and Tree Strucuture

In this paper, a new design technique for low power multiplier is introduced. This technique utilizes the bypassing method to minimize the switching activities and tree structure decrease the critical path. The design of circuit uses the standard TSMC 0.18mum technology. According to the simulation results, the proposed multiplier design can obtain more power savings than those of counterparts and achieve smaller power-delay product