A High Performance and Programmable Decoder VLSI for Structured LDPC Codes

We have developed a high performance and programmable LDPC decoder VLSI for decoding structured LDPC codes. In this paper, the architecture of the decoder and the structured parity check matrices are described along with the quantization method. We adopt floating point (FP) quantization method in check node processors so as to shrink down the complexity of look up tables (LUTs) of the Gallager function, and avoid performance degradation. Finally, simulation results show that the FP quantization method achieves high performance for wide range of code rates