SCFL static frequency divider using InAIAs/InGaAs/InP HEMTs

38.6-GHz operation of an SCFL static binary frequency dvider is achieved using 0.1-μm-gate InAIAs/InGaAs/InP HEMTs with an InP-recess-etch stopper. This is the highest operation frequency for static frequency dividers using FETs, as far as we know. In addition, propagation delay time of an SCFL inverter estimated from a ring oscillator is 6.6 ps/gate. The tranmission delay due to interconnection lines is investigated by taking account of travelling wave effects. Delay time analysis for above circuits proves that the transmission delay is much larger than the parasitic charging delay and as much as the intrinsic gate delay in such high speed. A comparative study shows the validity of the transmission delay and LC-line approximation, and reveals the importance of shortening signal path length and matching impedance between driver circuits and interconnection lines in ultra-high-speed operation.