Optimization of the Output Circuits of Power FETs Based on the Mismatch Power Penalty

A new approach to the optimization of the output circuit for a power FET is proposed, whereby the quantity maximized is directly the saturated power delivered by the device rather than the return loss referenced to the optimal load impedance for power. Thus, the power performance of the FET is more realistically represented and additional information is obtained on the power margin necessary for broadband operation.