SIMD Optimizations in a Data Parallel C

SIMD programs can devote substantial time to manipulating the underlying hardwares context registers status bits that determine whether processors in the SIMD array execute or skip the current instruction. This paper describes two optimizations, implemented in a compiler for a data parallel C, that reduce the overhead of manipulating and accessing context registers. The first optimization uses observations about a program's nesting structure to eliminate context register save/restore operations performed by guarded parallel control constructs. The second uses two-version code to eliminate context register acceaaes performed by individual instructions.