Parallelized VLSI Architecture of Single Stack based List Sphere Decoder

In this paper, we proposed a revised scaled-QR decomposition and corresponding VLSI architecture for the List Sphere Decoder(LSD). This architecture uses real-valued channel matrix and received vector. The average decoding latency is related to the number of the parallelized Partial Euclidean Distance(PED) calculation units. The trade-off relationships between latency and resource usages are analyzed and the reasonable number of calculation-unit is selected in the LSD architecture. By using the revised scaled-QR decomposition, the order of PEDs from the same parent nodes are fixed. This eliminates the sorting operations at each step. The average decoding latency of 4x4 64QAM is 160 clocks and that of other modulations are also analyzed.