Large Dynamic Range Accurate Digitally Programmable Delay Line with 250-ps Resolution

This paper presents a design of large dynamic range accurate digitally programmable delay line with 250-ps resolution on a single field programmable gate array (FPGA) chip. This design adopts time-to-digital conversion (TDC) technology, counter-based delay technology and small range digitally programmable delay line technology. When working with an oscillator with frequency accuracy of plusmn1 ppm, and when the delay range is within 0~0.1 ms, the delay accuracy of our design can reach plusmn350 ps