2.5 Gbit/s PRBS Generator and Checker

A novel approach in the implementation of a high-speed linear-feedback shift register (LFSR) using a single D-flip-flop is presented. A PRBS data generator and checker using discrete-logical devices are presented as an example. Due to the discrete-logical components used, special device-interconnection techniques must be used to reduce the signal-integrity problems and optimize the device interconnection for optimal system performance