Evaluation of Dual-Rail CMOS Logic Styles for Self-Timed Circuits

This work evaluates different CMOS logic families for asynchronous circuit design. The comparison is focused on self-timed circuit using four-phase protocol and dual-rail encoding in functional blocks with completion detection. Seven single-output and three multiple-output logic families were compared through electrical simulations taking into account both 0.13μm and 90nm CMOS technologies.