An Energy-Efficient 32-bit Multiplier Architecture in 90-nm CMOS

This paper describes an energy-efficient 32-bit multiplier based on a modified Booth-encoding scheme in a 90-nm CMOS technology. Further power-performance and area comparisons are presented, between the proposed architecture and a conventional Wallace tree based multiplier. Simulation results shows 47 % better energy-efficiency at the same delay and 24% lower area compared to the conventional multiplier