Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite

SoCs will soon have to integrate tens of complex system functions, each with their own optimal balance of performance, flexibility, energy consumption, communication, and design time. The traditional model of a (configurable) general-purpose processor core with a number of hardware accelerators no longer suffices. Application-specific instruction-set processors (ASIPs) can offer the right balance for each system function, and thus form the basis of new generations of multi-core SoCs. This presentation introduces Chess/Checkers, a retargetable tool suite available from Target Compiler Technologies, enabling the design of ASIPs in multi-core SoCs. Chess/Checkers offers fast architectural exploration, hardware synthesis, software compilation, inter-ASIP communication, and verification. The tools support a broad range of architectures, from small microprocessors, over DSP dominated cores, to VLIW and vector processors