Signal Integrity Impact of Ultra Low Power IO Initiatives

I/O power represents a sizeable portion of the overall power budget on a low power mobile platform. Significant fraction of that I/O power is used to ensure signal integrity on the high speed buses. While there is flexibility to trade off I/O power consumption against signal quality on Intel's current mobile and sub-note platforms, inefficiency still exists on wide I/O buses such as FSB and DDR2. In this paper, we will outline two novel bus termination schemes that can significantly reduce FSB and DDR2 I/O power consumption by further trading off signal quality on the new low power IA (LPIA) ultra small PC (UMPC) platforms