Noise Analysis of Time-to-Digital Converter in All-Digital PLLs

In an all-digital PLL architecture the conventional phase-frequency detector is replaced in part by a time-to-digital converter. This paper presents an exact analysis of the mechanism by which reference clock jitter and/or supply/substrate noise are converted into TDC noise that is injected into the ADPLL loop. The cases of white and sinusoidal noise are considered and the analytical results are compared with simulations