A Low-Power Routing Architecture Optimized for Deep Sub-Micron FPGAs

Signal propagation delay and leakage power dissipation of FPGAs mainly depend on the routing architecture. In this paper we propose solutions; adopted in an embedded FPGA developed both in 90nm and 65nm STM technology, which minimize the subthreshold current of the switch and connection blocks. Our approach leads to a reduction of more than one order of magnitude of standby leakage, up to 62% of active leakage of the routing architecture, having a small impact on signal delay, without silicon area increase