A dual-band triple-mode SoC for 802.11a/b/g Embedded WLAN in 90nm CMOS

An 802.11a/b/g-compliant SoC integrates a WLAN system, comprising a dual-band RF transceiver and PHY, MAC and ARM processor units, in 90nm CMOS. Challenges of SoC integration in 90nm CMOS and the mitigation techniques are discussed, along with circuit design techniques to optimize RF performance in 90nm. For 54Mb/s signals, the receiver sensitivity is -75dBm/-72dBm at 2.4GHz/5GHz, where the transmitter achieves an EVM of -35dB/-32dB at 0dBm output power