ECHO2, a multi-channel, single-chip, VLSI ECHO canceller with embedded TMS320C10 DSP

The design of a multi-channel, single-chip, adaptive echo canceller for T1 and E1 long-distance telecommunications networks is described. The ECHO2 chip required a novel architecture to achieve the throughput necessary to process multi-channels and end-paths of up to 128 msec delay. The design was implemented in Texas Instruments TLM CMOS EPICIZ 1 /spl mu/m process and TSC700 standard cell technology. Several MegaModules were used including a TMS320C10 cDSP, two 16 by 16 Multiplier-Accumulators and 2 Compiler Cell RAMs.<
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