Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging

As Moore's law is loosing steam, one already sees the phenomenon of clock frequency reduction caused by the excessive power dissipation. New technologies that will completely or partially replace silicon are arising, and new architectural alternatives are necessary. Reconfigurable fabric appears to be one of these solutions, and has shown speed ups of critical parts of several data stream programs. However, the wide spread use of reconfigurable computing is still withhold by the need of special tools and compilers, which clearly preclude software portability and reuse of legacy code. Based on all these facts, this work proposes a coarse-grain dynamic reconfigurable array, tightly coupled to a traditional RISC machine. Besides taking advantage of using combinational logic to speed up the execution, dynamic analysis of the code at run time was implemented to reconfigure the array, maintaining full software compatibility. Using the Simplescalar Toolset together with the embedded benchmark suite MIBench, meaningful performance improvements (up to 3 times of speed up) were shown, thanks to the implementation of the proposed approach