A multi-FPGA prototype of a DS1/HDSL synchronizer and desynchronizer prior to ASIC fabrication

As the speed and complexity of today's ASICs continues to grow, conventional prototyping techniques for algorithm verification begin to break down. A novel implementation of DS1/HDSL synchronizer and desynchronizer utilizing an array of four FPGA devices to verify algorithm performances prior to ASIC fabrication is described. The utilization of FPGA devices for ASIC prototyping can significantly reduce the risk, cost, and time-to-market involved with complex ASIC devices.<
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