On the implementation of an efficient performance driven generator for conditional-sum-adders

The authors present data structures and an efficient algorithm realizing efficient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and t/sub n/, the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay /spl les/t/sub n/, if such a circuit exists.<
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