Computer-aided technique for optimal design of defect-tolerant VLSI with built-in redundancy

Methods for taking account of the redundancy influence on the VLSI yield are developed. Using some fundamental redundancy arrangement methods, the interrelation between parameters of initial units and redundant hardware is discussed. On this basis, the generalized design approach is proposed. It can be adapted to demands of application-specific redundant unit design. Based on this approach the program PRIDE is developed. PRIDE provides automatic yield estimation and supports the redundancy logic design.<
>