Low Complexity Rake Receiver and Channel Estimator Implementation for DSSS-CDMA Systems

In this paper the implementation of a low complexity Rake receiver (RR) and channel estimator (CE) for direct sequence spread spectrum (DSSS) systems is presented with main scope to provide adaptability in receiver parameters while keeping the complexity at low levels. The trend in communication systems is towards dynamically adjusting system implementations that can adapt their structure to the continuously changing transmission characteristics. Following this trend we propose an architecture that is based on the spreading factor of the system, which controls the number of the taps that the CE and the RR will use depending on the current channel conditions. Moreover, based on a resource sharing approach of the main system components, that yet meets the standard bit rates, low complexity is achieved avoiding otherwise necessary complex structures such as complex multipliers. Furthermore we implement the proposed system on FPGA that gives us the ability to measure performance in terms of bit error rate (BER) in addition to that of power dissipation and area. Thus the performance of the system is compared with the performance of a high level system simulation of the same system, accomplishing the same BER levels. Finally the system implemented on a Xilinx Spartan-3 MB board occupies 56% of the total slices and consumes 103.45 mW with a 5 V supply