A Study of the As-Processed and Generated Leakage Paths in Al2O3-Based Dielectric Stacks for Nonvolatile Memory Applications

Continued shrinkage of floating gate devices requires scaling of the tunnel and/or interpoly dielectrics. This leads to increasing leakage currents that jeopardize the nonvolatile memory retention requirements. High-k materials are natural candidates to enable further scaling of the tunnel/interpoly dielectrics. In this paper, we present an analysis of the defects in Al
₂
O
₃
-based stacks. It is found that stacks with a deposited bottom SiO
₂
layer follow a two-step path generation trend, while the presence of a thin interfacial layer leads to a weaker path creation. Furthermore, the effect of the post-deposition anneal is also discussed