Extrinsic, Parasitic Capacitance Contributions of MOSFETs, their Impact on Performance, and their Modeling

We study layout dependent parasitic capacitance contribution of MOSFETs with 3-dim simulations, and show, that these capacitance contributions are for narrow, short devices comparable to intrinsic contributions. We show that the performance of 65-nm technology is strongly affected by these components, and have therefore been modeled correctly in circuit simulations. We propose a methodology how to accurately and consistently model them in a design flow. The methodology is validated with ring oscillator measurements