A High Performance pMOSFET with Two-step Recessed SiGe-S/D Structure for 32nm node and Beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe -source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved comparing with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at |V
_dd
| of 0.9V, I
_off
| of 100 nA/μm (552 μA/μm at |V
_dd
| of 1.0V). Furthermore, by combining with V
_dd
scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.