A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers

A 10bit SAR-ADC implemented in a 1.2V 0.13mum CMOS with 1V
_ppdiff
FS, based on capacitive-charge redistribution can be programmed with F
_s
up-to-6MS/s, guaranteeing an ENOB>9b with a SFDR>74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoMap1pJ/conv. Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200muW and the FoMap0.1pJ/conv. This appears an attractive solution for embedded ADC