Based on deep submicron under timing sensitive region clock tree reconstruction strategy

This paper presents a kind of optimization strategy which is aiming to optimize the clock tree in the timing sensitive region. By traversing through the clock tree, the timing sensitive region was found out. Then delayers and buffers can be added to or removed from this region according to the cases of single unassociated clock paths and multiple correlated clock paths. Meanwhile, the speed of transmission on data paths can be properly changed to eliminate the timing violations in the timing sensitive region. Furthermore, this optimization strategy is verified by experiment results at the end of this paper