A CORDIC Demodulator Platform for Digital-IF Receiver

A reconfigurable CORDIC demodulator platform and design method for digital-IF receiver is presented. A 2-level FSK demodulator for family network is implemented and tested on that platform with Xilinx VirtexII XC2V1000-4FG256 FPGA. The 2-level FSK noncoherent detector is designed based on counting the zero crossing points using new noise elimination technique. Synchronization control information is extracted from the amplitude signal through setting protection parameters. The output BER is 0.01% for input SNR of 1dB with frequency offset of 0.1MHz