A Double-Edge-Triggered Phase Frequency Detector for Low Jitter PLL

A double-edge-triggered phase frequency detector (dec-PFD) with modified true single phase clock D flop-flip (TSPC-DFF) is presented in a 0.35-mum CMOS technology. Due to a dead zone of 15 ps and three-state property, the dec-PFD can work up 1.5 GHz with decreased phase errors and jitter. The power consumed at 100 MHz is 0.74-mW from a 3.3-V power supply. The maximum frequency, phase characteristics and power consumption are simulated and compared with other phase frequency detectors (PFD's)