Low Power Wide Dominos Design in sub-65nm CMOS Technologies

Two novel low power wide OR domino designs are presented in this paper. With the same delay time, the two designed dominos decrease the active power by 8.92% to 17.25% and 13.79% to 25.84% as compared to the standard dual V
_t
dominos in a 45nm CMOS technology. In the meantime, the total leakage current is reduced significantly at two typical die temperatures