Implementation and electrical characterization of CMOS single-transistor charge-modulation pixel structure

This paper describes the implementation of a single-transistor (1T) charge-modulation pixel structure. It consists of a NMOS transistor with specific channel implant in a floating P-well. This same transistor can be operated for photosensing, charge storage, integration, readout and reset. A 2.2 mum pixel pitch array has been designed and fabricated in a 0.13 mum CMOS process. Testing results show a charge-voltage conversion factor of 35 muV/hole, and a charge storage capacity of 6200 holes without lag retention. They also confirm that the use of specific channel implant suppresses effectively Si/SiO
₂
interface trapping noise to achieve a temporal noise of 200 muV