Programmable Digital Frequency Multiplier

A programmable digital frequency multiplier with wide multiplication factor range and low lock time is presented. A digital algorithm is used to generate output frequency and an inbuilt PVT compensation mechanism ensures good frequency stability if there is any change in voltage and temperature during circuit operation. The circuit has been designed in 90nm CMOS process for input reference frequency of 32.768 KHz and multiplication factor range of 128 to 1023. The silicon results show less than 2% of average frequency error at maximum multiplication factor.