Benchmark Circuit Complexity Validation using Binary Decision Diagram Characteristics

It has been shown that when binary decision diagrams (HDDs) are formed from uniformly distributed random Boolean functions (BFs), the average number of nodes in the BDDs is in a simple relation to the number of variables and terms in the BFs. In the present work, the node counts for BBDs formed from ISCAS benchmark circuits are examined and compared to the results for random BFs. The model for random BFs is shown to have strong descriptive power for the benchmark data. Therefore, the model is promoted as a method of predicting, for a given BF, circuit complexity measures such as the area of a VLSI implementation