Fault Modeling and Detection for Drowsy SRAM Caches

With the introduction of the drowsy cache design technique (Kim et al., 2004), new fault behaviors appear and more restrictive design rules must be applied to the chip fabrication process. In this research, we simulate all possible spot defects (SDs) under normal mode and drowsy mode in different resistance regions using HSpice. Six new fault models appear with the introduction of drowsy mode for memory arrays. When we derive a march algorithm for the new fault models of this low-power cache, several simplification rules are utilized to reduce the test complexity. As a result, we develop a march algorithm which can detect all SDs in either data caches or instruction caches. Since some faults occur only in drowsy mode, a built-in self-repair (BISR) scheme is developed. By utilizing BISR, the cache can still work even if some cache lines fail to work in drowsy mode