Seamless Integration of SER in Rewiring-Based Design Space Exploration

Rewiring has been used extensively for optimizing the area, the power consumption, the delay, and the testability of a circuit. In this work, we demonstrate how rewiring can also be used for reducing the soft error rate (SER). We employ an ATPG-based rewiring method to generate functionally-equivalent yet structurally-different implementations of a logic circuit based on simple transformation rules. This rewiring capability, along with an off-the-shelf method for assessing the SER of a circuit, enable the integration of the SER in a unified search algorithm that iteratively evolves the design in order to satisfy a given set of objectives. Experimental results on ISCAS'89 and ITC'99 benchmark circuits verify that rewiring can indeed be successfully used to reduce the SER of a circuit and, thus, it facilitates a design-space exploration framework for trading off area, power consumption, delay, testability, and SER