Testing of UltraSPARC T1 Microprocessor and its Challenges

This paper presents the testing methodology of the UltraSPARC T1 microprocessor and the challenges to productizing the industry's first 8 cores and 32 thread microprocessor. The challenges include effectively testing 8 individual cores that share common functional blocks (L2 cache, cache crossbar, floating point unit), reducing 8times conventional production test time and tester memory while achieving the same coverage, and productizing 6 core or 8 core devices at the targeted frequency. Highlights of DFT features designed to overcome the challenges are presented followed by a production flow together with key learning and future improvement plans