FPGA Implementation of Expandable RSA Pubic-Key Cryptographic Coprocessor

In order to make the typical Montgomery's algorithm suitable for various lengths RSA, this paper proposes a scheme for an expandable RSA coprocessor. This design allows for cascading the hardware of process elements when larger modulo are required. The proposed design uses optimized Montgomery's modular multiplication algorithm. The proposed architecture has distinctive features, i.e. not only the computation speed is significantly fast but also the hardware overhead is drastically decreased