Phase Noise Optimization of A Symmetric CMOS LC VCO

A new approach to the design of CMOS LC-tank VCO with flicker noise upconversion optimization is proposed. The key idea is to get good phase noise performance using a symmetric and balanced circuit, which can be realized with equal transconductance and approximately equal parasitic capacitance of PMOS and NMOS transistors in the complementary cross-coupled LC VCO. The linear-time variant mode is used for prediction of the phase noise performance in the I/f
³
region. The impact on the phase noise of employing the equal transconductance and approximately equal parasitic capacitance of PMOS and NMOS transistors is analyzed. Moreover, the effect of the tail current for the reduction of phase noise is addressed. Simulated phase noise of -95.16 dBc/Hz at 100 kHz offset for the modified VCO, is compared with the simulated phase of -93.68 dBc/Hz at 100 kHz for the normal complementary cross-coupled VCO. The two LC VCOs are realized in 0.18 mum CMOS process with a 3 V power supply