A Fast Multiplierless Architecture for General Purpose VLSI FIR Digital Filters

A multiplierless algorithm for calculating the convolution of a Finite Impulse Response (FIR) digital filter is presented. The algorithm is based on the partial slicing of input data vector words and performing the convolution in a distributed fashion. A fast, flexible and hardware efficient architecture for implementing the algorithm is described. Simulation results of the prototype one tap filter are presented, demonstrating the high speed capability of the architecture.