A Novel Technique for Improving the Linearity of MOS Sampling Switch

A novel technique is proposed to improve the linearity of the MOS sampling switch (SW) by generating a replica transistor with the same threshold voltage as the sampling transistor. And it is obtained by forcing the replica transistor to operate in the triode region with the help of resistive voltage divider. The circuit has been implemented in chartered 0.35 mum standard CMOS technology. The proposed switch achieves a spurious free dynamic range (SFDR) of 110 dB for a 30 MHz, 1 Vp-p input signal, sampled at a rate of 80 MS/s, about 10 dB over the conventional switch, and the on-resistance variation is reduced by 90%