A Verilog Mixed Signal Model of a 10-bit Pipeline Analog-to-Digital Converter

A mixed-signal model of a 10-bit pipeline ADC is developed using the Verilog language. Transient results for individual cells and the overall converter are calculated by solving the characteristic differential equations using an event driven forward Euler numerical solver. The model includes nonlinearities within the amplifier such as capacitor mismatch and slew rate limiting. Post-processing is done in Matlab. The overall goal of this work is to develop a mixed-signal model to verify and identify design flaws based on ADC input/output tests