Advanced Process Modules for (sub-) 45nm Analog/RF CMOS - Technology Description and Modeling Challenges

The new process module and device architecture options emerging for (sub-) 45nm CMOS lead to both opportunities and challenges for analog/RF circuit design. A survey is given describing the advanced process modules for competing architectures (planar bulk CMOS versus FinFETS), for different gate stacks and mobility enhancement techniques. Challenges for compact modeling are identified