Analysis of a Two-Bit Frequency Discriminator in an All Digital Phase Locked Loop for RF-Modulation and RF-Frequency Synthesis

A key issue in pushing the digitization of phase locked loops (PLLs) for RF transmitters is the realization of proper phase/frequency detectors in the digital domain. This paper presents a simulative analysis of the properties for and requirements of a two-bit frequency discriminator used for digitization of frequency in all digital PLLs (ADPLLs) with two-point modulation. Effects due to reference clock jitter in one-bit and two-bit frequency discriminators are treated. Furthermore, measurement results for the synthesis mode of the ADPLL used in multi-mode capable terminal are given