Sub-1/4-/spl mu/m dual-gate CMOS technology using in-situ doped polysilicon for nMOS and pMOS gates

A new dual poly-Si gate CMOS fabrication process is proposed. The incorporated technology features a boron-penetration-resistant MBN gate structure for pMOSFET's, and a dual poly-Si gate CMOS process involving separate depositions of in-situ doped n/sup +/ and p/sup +/ poly-Si for the nMOS and pMOS gates, 0.2-/spl mu/m CMOS devices with 3.5-nm gate oxide have been successfully fabricated. The advantages of the new process are demonstrated on these test devices. A CMOS 1/16 dynamic frequency divider fabricated by the new process functions properly up to 5.78 GHz at a 2-V supply voltage.<
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