A static technique for high-speed CMOS state machine design

This paper presents a technique for designing CMOS high-speed state machines with a clock frequency ranging from DC to greater than 130 MHz in 1.2-/spl mu/m technology. This technique applies weak feedback to known high-speed dynamic circuits to achieve both static and high-speed capability. Two-phase nonoverlapping clocking is used to eliminate any possible races. Propagation delays of critical paths are minimized by performing their logic functions within the master stage of the flip-flops.<
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