A Geometric Synthesis Method of Three-Input Majority Logic Networks

A simple methods is developed for the synthesis of any arbitrary logical network by three-input majority gates. The methods is based on a generalization of a geometric interpretation of Boolean functions and on the fundamental property of a 3M gate; if there are the same signals on two inputs (representing logical O or I), then the output of the gate is independent of the third input signal. This represents therefore a ``don't care'' condition. In the synthesis procedure all functions are represented by a direct n-cube diagram. For recognition of various topological forms (k-dimensional subcubes, s-multiple stars) graphical-mechanical aids (contact and directional grids) can be used. The method of reduction of arguments after each synthesis step is shown and minimal majority expansions of all types of two and three-argument functions are tabulated. The problem of the time delay and/or ``symmetry in time'' in 3M-gate networks is treated in some detail.