Integration of step-edge grain boundary Josephson junctions with YBCO multilayers for electronics applications

We discuss our multilayer YBCO process which uses step-edge junctions. Key issues are dielectric defect density, wiring layer critical current over edges of underlying features and junction critical current uniformity. We have demonstrated an average defect density of about 450/cm/sup 2/ over many wafers. Wiring critical current exceeds 1 mA//spl mu/m of line width. We have demonstrated SQUIDs at 77 K using this process.<
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