High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation

Two dimensional discrete cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems. In this paper, efficient architectures with parallel and pipelined structures are proposed to implement 8times8 DCT and IDCT processors. In which, two 8-point DCT/IDCT processors with dual-bank of SRAM (128 words) and coefficient ROM (6 words), two multiplexers, and control unit are involved. The kernel arithmetic unit (AU) is designed by using CORDIC arithmetic. The proposed architectures for 2D DCT/IDCT processors not only simplify hardware but also reduce the power consumption with high performances