Experimental Study on the Damage Effects of Integrated Circuits Stressed with ESD EMP

Several RC (resistance and capacitance) combinations were adopted in ESS-AX200 ESD simulator to generate different ESD pulses. And the pulses were injected into an integrated circuit. The damage effects of the integrated circuit stressed with these pulses were investigated. Results showed that the current passing through the device will increase when the discharge voltage increases. The relationship between the peak energy absorbed by the IC chip and the discharge voltage can be modeled as the bell-shaped Gaussian function. The failure thresholds of the IC were the same order of magnitude and were found to vary by less than a factor of two